Modern electronics rely heavily on memory. This is because memory is central to a vast majority of computing operations. For instance, running an application on a device, such as a cell phone, a tablet, personal computer or other devices, will require the utilization of memory. This memory can be in the form of persistent storage, such as solid state drives (SSDs), hard disk drives (HDDs), or even tape drives. However, persistent storage tends to be slower than non-persistent storage such as random access memory (RAM).
However, simply implementing DRAM is insufficient to continue to meet ongoing and ever advancing computing demands. Thus, to improve throughput of memory devices including DRAMs, the speed at which these devices communicate continues to increase. Unfortunately, increasing the speed with which a DRAM device operates alone causes undesirable problems. One problem is an increased likelihood that signal noise or some other factor will cause the incorrect transmission of signals between a memory accessing apparatus and a memory device. In this regard, the DRAM specification for DDR4 (fourth generation double data rate DRAM) specifies support for cyclic redundancy checking at a DDR4 memory apparatus against a cyclic redundancy check value appended to the end of a burst write transmission.
Upon completion of a burst command the memory will compute a cyclic redundancy check value, and compare that with the received redundancy check value. If the received and the computed redundancy check values do not match, the memory will send a notification to the requesting apparatus indicating that cyclic redundancy check failed and thus that there was an error in transmission.
Unfortunately, even though memory devices that comply with the DRAM specification will provide a notification of an error, conventional implementations are unable to pinpoint the specific burst command that had failed to pass the cyclic redundancy check.
Therefore, what is need is an approach to address the shortcomings of memory devices such as those constructed to be compliant with the DDR4 specification.